By Douglas Perry
* Teaches VHDL by way of instance * contains instruments for simulation and synthesis * CD-ROM containing Code/Design examples and a operating demo of ModelSIM
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Additional resources for VHDL: Programming By Example
Its value is not changed until the process has completed execution of all sequential statements contained in the process. In fact, if signal b is a ‘1’ value, then whatever garbage value the signal had when entering the process will have the value 2 added to it. A better way to implement this example is shown in the next example. The only difference between the next model and the previous one is the declaration of muxval and the assignments to muxval. In the previous model, muxval was a signal, and signal assignment statements were used to assign values to it.
In fact, the value 0 is scheduled in an event for the next simulation delta because no delay was specified. When the second statement: IF (a = ‘1’) THEN muxval <= muxval + 1; END IF; Sequential Processing 45 is executed, the value of signal muxval is whatever was last propagated to it. The new value scheduled from the first statement has not propagated yet. In fact, when multiple assignments to a signal occur within the same process statement, the last assigned value is the value propagated. The signal muxval has a garbage value when entering the process.
The next example shows more complicated signal assignment statements and demonstrates the concept of concurrency in greater detail. In Figure 2-2, the symbol for a four-input multiplexer is shown. ALL; ENTITY mux4 IS PORT ( i0, i1, i2, i3, a, b : IN std_logic; PORT ( i0, i1, i2, i3, a, q : OUT std_logic); END mux4; ARCHITECTURE mux4 OF mux4 IS SIGNAL sel: INTEGER; BEGIN WITH sel SELECT q <= i0 AFTER 10 ns WHEN 0, q <= i1 AFTER 10 ns WHEN 1, 18 Chapter Two MUX4 Figure 2-2 Mux4 Symbol. I0 I1 Q I2 I3 A B q <= i2 AFTER 10 ns WHEN 2, q <= i3 AFTER 10 ns WHEN 3, q <= ‘X’ AFTER 10 ns WHEN OTHERS; sel <= 0 WHEN 1 WHEN 2 WHEN 3 WHEN 4 ; END mux4; a a a a = = = = ‘0’ ‘1’ ‘0’ ‘1’ AND AND AND AND b b b b = = = = ‘0’ ‘0’ ‘1’ ‘1’ ELSE ELSE ELSE ELSE The entity for this model has six input ports and one output port.